
350 Cable Survey System
DPN 402197 © TSS (International) Ltd Page 6 of 26
2. Processor Core (see drawing 401103-2).
Data from the ADC Interface arrives at the Digital Signal Processor (DSP) U1.
The DSP operates with four parallel bytes of zero wait state SRAM forming 32-bit
words. It reads its program from EPROM U12 at power-on and copies it into RAM for
execution in a manner similar to a PC ‘booting’ from a disk.
Byte-wide E
2
PROM U11 provides non-volatile parameter storage, and PLD U5 imple-
ments primary decoding.
SCC devices U17 and U18 handle communications to and from the SEP: U17 han-
dles communications with the SDC and the direct communications from the sub-sea
altimeter. This version of the SEP does not use U18.
Buffer U57 provides the gain control signals for the pre-amplifiers and the ADC con-
trol signals APD, DPD and CMODE.
3. Communications Interface (see drawing 401103-3).
U19 and U20 opto-isolate the current-loop signals that pass between the SEP and the
SDC.
U22, U23, U24 and U25 respectively control the RS232, 2-wire and 4-wire current-
loop communications. The settings of links LK1 to LK5 select among four options (see
sub-section 4.2.2.1 for instructions to change the communications method). Note that
the current version of SDC does not support the fourth method, RS422 communica-
tions.
Opto-isolators U28 and U29, and ICs U31 and U32 support direct communications to
the SEP from an altimeter.
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